In this graphic, the relation between the needed die area of an integrated circuit to implement a function and the die area needed to protect the circuit is demonstrated. Due to the continuous effort to reduce the die area to save costs and the reduction of the gate oxide thickness, the chip size is now less than the 65 nanometer mark shown in the graphic. The disadvantage of the minimized structure is the increased vulnerability to ESD strikes, which results in the die area needed to protect the circuit outgrowing the size of the function itself. Therefore, external protection is strongly needed to protect the circuit against ESD strikes.