The hard memory controller in the HPS provides access to external DDR2, DDR3, and LPDDR2 memory devices. The controller has four ports dedicated to the processor, and can share up to six ports with logic in the FPGA. The multiport front end schedules pending memory transactions based on user-provided priorities. Transactions can be prioritized by port and by burst. Under program control, high-priority traffic can bypass the queue to minimize latency. The memory controller provides high memory bandwidth, high clock rate performance, and run-time programmability. It automatically reorders data to reduce row conflicts and bus turnaround time by grouping reads and writes together, allowing for efficient traffic patterns and reduced latency.