Since the HPS is on the corner of the device, I/O pins physically closest to the HPS are used for its memory and peripheral interfaces. The rest of the pins are used as general-purpose FPGA I/Os and for transceivers. Peripherals are assigned to the HPS I/Os as part of the boot process. Intel® provides a tool to let designers make the assignments. The only exception is the I/Os dedicated to the DRAM controller. Peripherals can also be routed into the FPGA fabric for connection to custom logic or FPGA I/O pins. FPGA logic can also be routed to unused HPS I/Os when appropriate.