Developers have multiple choices in configuring and booting the SoC device. This diagram shown here illustrates independent FPGA configuration and processor boot functions – just as though they were two independent discrete devices. The FPGA can configure from the usual serial and parallel flash devices, and can now configure from QSPI flash and even over the PCI Express interface. Designers may also boot the processor first, and then configure the FPGA. Using this method, the processor can configure, reconfigure, and even partially reconfigure the FPGA under program control. The HPS contains several flash memory interfaces that can be used for processor boot code or designers may configure the FPGA first. Logic in the FPGA provides a custom interface through which the processor fetches its boot code. This is useful for implementing secure boot modes, or when processor code is provided through a custom backplane or proprietary interface.