The SoC FPGA is low power by design. The dual-core Cortex®-A9 processor with both CPUs running at 800 MHz delivers 4,000 MIPS while consuming less than 1.8 W. The HPS and FPGA are on independent power planes, letting designers shut down the FPGA when needed for low-power operation modes. The processor has access to the PLLs and clock dividers, and can reduce power consumption by reducing clock frequency and gating clocks to unused portions of the HPS. An example is by shutting down one of the CPUs. The processors can also go into low-power sleep modes, and then wake on an external event or interrupt. The memory controller power management features allow self refresh, partial array self-refresh, power down, and for LPDDR2, deep power down.