Shown here is a more detailed block diagram of the SoC FPGA. The portion in blue is the HPS, and it contains the dual-core processor, each CPU with its own floating-point unit, NEON coprocessor, and L1 caches. The processors share a 512-kB L2 cache and a rich set of peripherals, including two triple-speed Ethernet ports, two USB on-the-go ports, interfaces to flash memory, general-purpose embedded peripherals such as UART, SPI, CAN, and I2C, and a shared multiport DRAM controller that supports DDR2, DDR3, and LPDDR2 – all with error correction code. A high-bandwidth interface connects the HPS and FPGA fabric. The processor has direct access to the FPGA configuration controller so it can configure the FPGA under program control. The light green portion represents the FPGA fabric. Intel®’s SoC FPGAs are based on the 28-nm Cyclone V and Arria V devices and inherit the low-power characteristics, 8-input ALM architecture, and fractional PLLs. They also inherit the hard IP blocks integrated in these new device families, including additional memory controllers, PCI Express, and variable-precision DSP blocks. These hard IP blocks consume less power, ease the design process, and provide more logic resources.