This slide shows the control loop cycle in time domain, with ISR code indicated by the yellow block and other code indicated by the blue. It is necessary to compute the cycle count of the ISR, in order to determine how fast the processor must be, in terms of what the processor delay can be. In this example the ISR delay calculates to a seventy seven cycle delay. What is shown linearly is the sample point, and an interrupt, followed by the ISRNs, and then a sample point on the output side. Also shown is the control loop delay, which is the goal in embedded systems, to minimize the control loop delay. The C2000 devices are proven to have very low control loop delays, and high sampling frequencies. High resolution PWMs minimizes the control loop cycle on a loop by loop basis.