This slide shows the sample to output delay, looking at a curve that goes from left to right. Shown on the top is the continuous time feedback signal, and below is the actual conversion. Time delays are imposed by the ADC and the control law computation. The line of desired control effort is the desired output. The line of effective control effort is indicated by the purple line, and the reconstructed signal is the blue line. The time delays are represented by the black arrows above. The goal is to minimize the time delays, to make the line of effective control as close to the line of desired control effort as possible.