This slide shows how Concerto™ is constructed. It is a dual core device, with a control system and a host system. The control system is a precision control, low-latency system. The host side is a 32-bit ARM Cortex™-M3, capable of running up to 100 MHz, with 256-512 K of dedicated memory. There is a 10/100 Ethernet MAC in the device, as well as USB On-The-Go, and SSI ports. Also included in the host are UARTS, I2C, and two CAN transceivers, all independent of the C2000 core in the system. The control subsystem, the C2000 core, is a traditional C28x core, running at up to 150 MHz. It does have floating point math capability, and includes the FPU engine. There is also the Virturbi math engine which is used primarily for power line communications applications. The standard C2000 communications include McBSP and SPI, plus there is an I2S and a UART for the C2000 device. There are eighteen PWM outputs on this device, with up to sixteen of those being high resolution capable, in the 100 nS range. This device has a shared analog bridge, with an integrated ten sensor analog input, a 12-bit, 10-channel ADC, two sample and holds, and a three channel analog comparator. Many times in a control system which is running with digital power, it is necessary to set an analog comparator as a trip point for the PWMs. If the processor for some reason loses control, an analog function must be able to trip the PWMs and shut the system down. TI has had this feature in the Piccolo and Delfino product lines, and has carried this through to the Concerto device, in which there are three analog comparators. These are directly tied to the analog input and the PWM output, and do not require interaction from either processor to trip the PWMs. These can be set as true analog comparators, as a safety mechanism, or a digital fuse for lack of a better term. The Concerto also has parity RAM which can be used to message back and forth between the two cores. The device has internal oscillators and can use an external oscillator if desired. With clock fail detection and correction if one clock becomes faulty the second clock can retain system redundancy while the first clock resets.