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Each receiver channel can be clocked by one of the two dedicated MPLLs associated with that quad. The CDR in each channel allows each receiver to align exactly to the data on that channel which minimizes or eliminates the affect of skew on bonded channels. Each MPLL provides two dedicated outputs to the transceivers, the CLK and CLK2x are additional outputs that can be used to feed the FPGA fabric. It is important to note that the MPLLs can only clock contiguous channels. Therefore, MPLL2 can drive channels two and three while MPLL1 drives channels zero and one, or MPLL2 can drive channels zero and one while MPLL1 drives channels two and three, but MPLL2 cannot drive channels three and one while MPLL1 drives channels two and zero.
PTM Published on: 2012-05-29
