In summary, the specific innovations for Cyclone® IV GX are the integrated transceivers that address most mainstream 3G applications, the integrated PCIe hard IP that supports x1, x2 and x4 lanes along with rootport and endpoint configurations, and the MPLLs and the resulting changes to the clock networks throughout the FPGA. The transceiver architecture is quad based and designed to easily and effectively share clocks. Each transceiver is full duplex, each channel consisting of a receive and transmit differential pair. The combination of clock sharing and full duplex enables the user to transmit and receive data at different rates for each channel. The transceiver clocking flexibility is further enhanced in the Cyclone® IV GX with clock/data recovery for each channel which allows the transceivers to borrow MPLL and GPLL clocking resources. This also allows the user to implement multiple independent protocols, lowering the total system cost.