Cyclone® IV devices have eight separate banks, each of which can interface to any I/O standard or external memory. Certain banks are optimized for highest performance for memory interfaces and LVDS communication. For example, top and bottom banks are optimized for memory interface performance and left and right banks are optimized for LVDS performance. Two additional registers in the I/O cell increase DDR interface performance by improving the write margin. Differential output buffers not only reduce board space required, but also eases PCB routing in applications such as the many high volume display column drivers. The Cyclone® IV GX transceivers have dedicated I/O pins and banks which are shielded from general purpose I/O for the best performance and signal integrity. Cyclone® IV devices allow selection of 25 Ω or 50 Ω series termination values. The user can also choose to have these values calibrated at power up before going into user mode. A periodic user mode calibration feature may be offered after device characterization. Adjustable slew rates can improve signal integrity by slowing down edge rates on non-performance critical I/O pins.