The transceiver architecture is largely based on the previous generations of transceivers. It is a quad based structure which means the transceivers are designed to easily and effectively share clocks. This enables easy channel bonding which allows the user to aggregate multiple lanes of data at slower data rates to create a faster data rate channel. A perfect example of this is XAUI, which aggregates four channels to create a virtual 10G channel. Each transceiver is full duplex, which means that each channel is comprised of a receive and transmit differential pair. The combined benefit of clock sharing and full duplex allows the user to transmit and receive data at different rates for each channel, a benefit specific to Intel's® integrated transceivers. In the Cyclone® IV GX, the transceiver clocking flexibility is further enhanced by independent clock/data recovery for each channel, allowing the transceivers to borrow MPLL and GPLL clocking resources, and even lending unused MPLL clocks to the FPGA fabric. This enhanced transceiver clocking allows the user to implement multiple independent protocols, lowering the total system cost.