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Cyclone-Slide2

Shown on this slide is a block diagram of the Cyclone® IV GX device showing the relational placement of the major blocks. The specific innovations for the Cyclone® IV GX are the integrated transceivers that address most mainstream 3G applications, the integrated PCIe hard IP that supports x1, x2 and x4 lanes along with rootport and endpoint configurations, and the MPLLs and the resulting changes to the clock networks throughout the FPGA.

PTM Published on: 2012-05-29