Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18 Slide 19 Slide 20 Slide 21 Slide 22 Slide 23 Slide 24 Slide 25 Slide 26 Slide 27 Slide 28 Slide 29 Slide 30 Slide 31 Slide 32 Slide 33 Slide 34 Slide 35 Slide 36 Slide 37 Slide 38 Slide 39 Slide 40 Slide 41 Slide 42 Slide 43 Slide 44 Slide 45 Slide 46 Slide 47 Slide 48 Slide 49 Product List
Cyclone-Slide26

The Cyclone® IV GX clock networks have been modified from the Cyclone® III to have up to thirty global clock networks feeding the FPGA fabric for devices offered in the F484 package and larger. Smaller devices have up to twenty global clock networks. As with the Cyclone® III, the GCLK I/O can be used as general purpose I/O and are highly recommended for use for high fanout signals such as resets or clock enables. Again, as mentioned previously, the MPLLs and GPLLs can be shared.

PTM Published on: 2012-05-29