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Cyclone-Slide5

The diagram on this slide shows the sub-blocks within both the PMA and PCS. Depending on the protocol implemented, the appropriate sub-blocks will be selected when the transceiver is instantiated through the Intel® MegaWizard®. In the case of a proprietary protocol, indicated as “basic mode” in the Intel® terminology, the data path can be customized in the PCS by specifically bypassing certain functions such as the byte serializer, deserializer, the 8b/10b encoder/decoder, the rate matcher and word aligner. The only required blocks in the PCS are the functions used for de-skewing data and buffering required to successfully interface to the FPGA fabric.

PTM Published on: 2012-05-29