This slide shows that MPLLs may also be shared with the FPGA core. Shown is the left half of the clocking architecture of larger devices that have eight transceivers. The top and bottom MPLLs provide three additional clocks to the global clock multiplexer and the middle MPLLs provide two additional clocks for up to twelve different clock frequencies that can be fed from these sets of PLLs. One item to note is that not all MPLLs and GPLLs can be shared. Only the adjacent MPLL can be borrowed by a quad and only one GPLL can be borrowed by a quad, but not both. It is also important to note that when the MPLLs are used to drive transceivers the clock outputs provided to the GCLK multiplexers have frequencies related to the M and N values required for the transceiver protocol.