Although many modern FPGAs do not explicitly state a power-up sequence, some still do, so check datasheets for specifics. A common requirement is to use a regulator with a soft-start feature to help limit in-rush current. If in-rush currents are not limited, it can cause the supply to glitch on startup and violate the monotonic rise requirement. In addition, it is best to pick a regulator with closed-loop regulation active during startup. The problem is that when using a synchronous regulator, the bottom FET can sink current, which pulls the output down. To prevent this, ensure the part features a diode emulation mode where the bottom FET does not sink current, thus preserving the monotonic rise. Different FPGA elements use this voltage to turn on sequentially, so the correct ramp of this voltage is essential for the adequate power-up of the FPGA. Elements turning on in the middle of ramp up also cause a load step on the power supply that needs to be handled without major transient disruption.