When using a switching regulator there are three basic techniques to reduce output ripple from a regulator. One common technique is to use an LDO or linear regulator. There are two effects at work here: power supply rejection ratio or PSRR, and the filtering characteristics of the input and output capacitors. One technique is to apply a switching regulator to step down the voltage to just above what is required by the FPGA, then use a linear regulator to step the voltage down to what is needed. In this way, power dissipation is minimized. Although effective, the major drawback is the additional cost and footprint. Keep in mind that PSRR is less effective at filtering very high frequency (above 1MHz) spikes. Another technique is to use an LC filter to low pass filter noise. One rule of thumb to size components at a ratio of inductance to capacitance of approximately one to ten to provide the maximum dampening. Adding a small value ceramic capacitor in parallel reduces high frequency spikes. A third possible technique is to use a ferrite bead. A rule of thumb is to choose one with the maximum impedance at the frequency of interest. Please consult the manufacturer’s datasheets for further details.