The PTM has so far shown how to solve different core voltage requirements, but will now look at circuits that require low noise power supplies. When low noise is mentioned, it really means a small peak-to-peak voltage ripple. This is because voltage ripple conducts into an FPGA’s sensitive analog circuitry, such as the phase-locked loops and manifests itself as jitter in the clock output of the phase-locked loop. High-speed serial transceivers also require very low voltage ripple as signal integrity can also be greatly affected due to jitter. Many designers use LDOs or linear regulators as, unlike switching regulators, these do not significantly contribute to voltage ripple. Unfortunately, linear regulators are not efficient and the resulting power dissipation may be unacceptable. As a rule of thumb, when power dissipation exceeds 1W, a switching regulator should be used. This limitation allows a linear regulator to be used to power auxiliary circuits, but is insufficient with the latest high-speed serial transceivers where current consumption can exceed 3A.