Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18 Slide 19 Slide 20 Slide 21 Slide 22 Product List
Powering FPGAs Slide 14
These efficiency curves show how switching frequency affects regulator efficiency. Regardless of the input voltage, the LM3670 with a 1MHz switching frequency has higher efficiency at 95% than the LM3671 with a 2MHz switching frequency at 90%. The increased alternating current losses occur due to the following reasons: gate switching loss, dead time loss, and the alternating current loss of the inductor. Gate switching loss involves turning the switch’s gate on, and the energy required for it. A higher switching frequency means that the gate is on more frequently in the same time period, thus consuming more energy. Dead time loss is the energy lost when dead time is enforced. During dead time, neither the high nor low side FETs are on in order to prevent shoot through (short-circuiting voltage in to ground). The energy is typically lost through the body diode or substrate. Alternating current loss of the inductor involves increasing the frequency. As the switching frequencies increase, the inductor’s equivalent series resistance also increases, which leads to higher losses. Note that at the lower frequency, a 10µH inductor is used instead of a 2.2µH inductor. So the higher switching frequency, the smaller the solution size.
PTM Published on: 2011-11-02