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Core-Slide9

The first is the 64-bit path to on-chip 100MHz Flash memory. The second is a 64-bit path to on-chip 100MHz SRAM. The third is access to a high-speed 32-bit wide, 50MHz internal bus, named Internal Main Bus 1. The CPU is bus master to the bus matrix with Flash, SRAM and Internal Bus 1 acting as slaves. Internal Bus 1 also gives the CPU access to the external bus pins through the Bus State Controller, or BSC, as well as to the on-chip peripherals through a Bus Bridge. The connection to on-chip peripherals will be seen in a moment.

PTM Published on: 2012-05-15