Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18 Slide 19 Slide 20 Slide 21 Slide 22 Slide 23 Slide 24 Slide 25 Slide 26 Slide 27 Slide 28 Slide 29 Slide 30 Slide 31 Slide 32 Slide 33 Slide 34 Slide 35 Slide 36 Slide 37 Product List
Core-Slide5

Now to examine the paths between the CPU core and memory. The RX is based on an enhanced Harvard architecture, with a 64-bit wide dedicated bus for instructions and a 32-bit wide dedicated bus for operands, or data. This is an extremely optimized arrangement. The longest RX instruction is 64 bits and the native data size is 32-bits, but options exist for 8-, 16-, and 64-bit data as well. The data can even reside at odd address boundaries to eliminate wasted space in expensive SRAM. Typically, the instruction bus is connected to Flash memory and the data bus to SRAM. But as will be seen later, it does not always have to be this way since RX has “enhanced” Harvard architecture.

PTM Published on: 2012-05-15