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Core-Slide37

In summary, this module has covered the RX CPU core and pipeline, the interfaces used by the core to talk to memory and peripherals and the unique instruction set of the RX that merges the best of CISC and RISC. It has also covered the flexible interrupt handling that allows one to craft low-latency service routines. Additionally, this module provided an overview of the single-precision floating point unit that gives the user number-crunching power in a microcontroller. And finally, this presentation covered the high-speed memory that makes sure all of these features flow through the chip at full speed.

PTM Published on: 2012-05-15