This discussion will start with the differences between Complex Instruction Set and Reduced Instruction Set Computer architecture, or CISC versus RISC. Beginning with CISC, where the ultimate goal is to have a small memory footprint, here are some key attributes of traditional CISC architecture: Generally, all instructions can access memory and many addressing modes, variable length instructions pack code tightly into program storage space, resulting in lower requirements for program memory size, and rich instructions add efficiency. This approach does have its drawbacks, however. CISC instructions can take many clocks to execute, are difficult to pipeline (reducing performance) and interrupt responses can be longer. Now this module will take a look at the attributes of RISC processors, where the goal is to achieve one clock per instruction. The instructions, as one would expect, are much simpler and fewer in number on a RISC. Access to memory is only through load and store commands. Instructions are in a fixed format with typically only one or two instruction lengths available. This results in a larger code footprint, but it does make pipelining easier which in turn makes it possible to achieve the goal of one clock-per-instruction. Wouldn’t it be great if one could take the best attributes of CISC and combine them with the best attributes of RISC? Well, RX does exactly that providing the best blend of both CISC and RISC. It capitalizes on the positive features of each while rejecting the negatives.