So far this module has discussed CPU access to extremely fast local Flash and SRAM memory, but the RX core can access slower memories and peripherals too. In this case there is a small pre-fetch queue to look ahead and pre-fetch instructions during idle bus cycles when executing from slower memory, such as external memory. This pre-fetch queue is four deep, and each stage is 64-bits wide. This means there can be as many as 32-, 8-bit instructions in the queue at one time. The pre-fetch queue helps to maintain a steady flow of instructions to the CPU, filling gaps during idle bus time while instructions are sequential. The queue also reduces stalls when the CPU takes a branch in instruction flow. If the target branch instruction is residing in the queue, there is no delay. If the target is not in the queue, the queue must be flushed and reloaded. The actual delay to refill the first entry into queue depends on the access time of these slower memories. And finally, there is a write buffer to prevent the CPU from stalling after writing to a slow external memory, or to a slow peripheral device. This buffer allows the CPU to carry on at full speed and not to wait for the write operation to complete. Now to examine how the RX CPU core fits into the entire system.