Notice that the Flash can be read at 100MHz, the same frequency as the CPU. This means the CPU will not stall while waiting to read instructions from Flash at 100MHz, even when the instruction is 64 bits wide. Also notice that the SRAM can be read, and written, at 100MHz to give the CPU full speed access for data. Now moving to the instruction pipeline. A pipelined architecture is absolutely necessary for any high performance CPU to reach that ultimate goal of executing one instruction in just one CPU clock cycle. The RX has a 5-stage pipeline, breaking up decoded instructions into many smaller parallel tasks, reducing the amount of sequential logic. A 5-stage pipeline enables the RX CPU core to be clocked extremely fast, in fact, the clock will be increasing to 200MHz in the future. The five pipeline stages are: Fetch, Decode, Execute, Memory access and Register Write-back. As one can see, on each CPU clock the instruction pipeline gets progressively filled, and by the 4th clock cycle, it is already possible to achieve one clock per instruction, or one CPI.  Looking closer at one individual cycle in the pipe one can see that the CPU can command both an instruction fetch and simultaneously access data in this same CPU clock cycle. If not for the Enhanced Harvard architecture, this concurrent activity would not be possible and would cause a pipeline stall.