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Core-Slide4

Here this module will examine the RX CPU core itself, the pipelined instruction path and the operand path. At the heart of the RX600 MCU is a 100MHz, 32-bit CISC CPU core seen here, capable of 1.65 Dhrystone MIPS/MHz. The CPU has sixteen 32-bit general-purpose registers, striking the optimum balance between performance and cost. There’s also a full single precision floating point unit tightly coupled to the CPU core, a multiply accumulate unit producing either a 48-bit MAC result in one-cycle, or an automatically repeating MAC producing an 80-bit result for very efficient DSP operations, a hardware multiply and divide unit, plus fast interrupt control, and an on-chip JTAG debugger with high-speed trace, and a Memory Protection Unit.

PTM Published on: 2012-05-15