The ARM7 core is a reduced instruction set computer (RISC) that provides high instruction throughput and real-time interrupts that MCUs require. This MCU utilizes a 3-stage pipeline in which an instruction is fetched, decoded, and finally executed. The ARM7TDMI core features a Von Neumann architecture in which a single path is used for both instructions and data, as opposed to a Harvard architecture that has separate paths for each. However, the LPC2000 family also has a data bypass buffer in the memory accelerator module (MAM) to reduce any potential bottlenecks of this path sharing.