In summary, the NXP LPC2300 and LPC2400 series feature Von Neumann architecture and Thumb mode on a 32-bit model, making a communications protocol stack the same size as on a common 8- or 16-bit architecture. They feature low power consumption due to various power options and reduction modes. The MAM was developed instead of a cache so the MCUs can execute at 72 MHz. Three levels of code protection restrict access to the on-chip Flash and three independent busses eliminate bottlenecks on the Von Neumann architecture. These devices have numerous on-chip peripherals, are fully USB 2.0 compliant, and have four clocks including the main oscillator, IRC, and RTC.