设置
快速交货
免运费
国际贸易术语
支付类型
市场产品
Slide 1
Slide 2
Slide 3
Slide 4
Slide 5
Slide 6
Slide 7
Slide 8
Slide 9
Slide 10
Slide 11
Slide 12
Slide 13
Slide 14
Slide 15
Slide 16
Slide 17
Slide 18
Slide 19
Slide 20
Slide 21
Slide 22
Slide 23
Slide 24
Slide 25
Slide 26
Slide 27
Slide 28
Slide 29
Slide 30
Slide 31
Slide 32
Slide 33
Slide 34
Slide 35
Product List
The on-chip independent Ethernet MAC is located on a second AHB bus with 16 KB of SRAM buffer and a dedicated DMA. This MAC supports most external 10/100 Ethernet PHY devices from 10 Base T to 100 Base T4. All of the LPC2300 and LPC2400 MCUs with Ethernet have a 10-pin Reduced Media Interdependent Interface (RMII). In addition to the RMII, the LPC2400 devices also feature a full 18-pin Media Independent Interface (MII) bus that is used to transmit, receive, and control for 4-bit data. The NXP Ethernet MAC IP is fully compliant with IEEE 802.3X PAUSE MAC Control protocol and employs full duplex flow control and half duplex back pressure, both which improve reliability of the Ethernet transmission.
PTM Published on: 2011-11-02
