The FT800 supports a common data communication scheme, regardless of whether the SPI or I²C interface is selected. A 4MB address space is utilized for graphic, touch, and audio controller registers as well as memory buffers for use with each controller. The memory map is defined in Section 5 of the FT800 Datasheet. The host reads and writes the FT800 address space using SPI or I²C transactions. Both interfaces use the same byte ordering. Multiple bytes are sent as “Little Endian”. For example, the REG_FREQUENCY register has a default value of 0x02DC6C00 after reset. When reading this value, the byte order on the MCU interface is:  0x00, 0x6C, 0xDC, 0x02. I²C transactions are encapsulated in the I²C protocol.  SPI data is sent by the most significant bit first, mode zero. For SPI operation, each transaction starts with SS_N goes low, and ends when SS_N goes high. There’s no limit on data length within one transaction, as long as the memory addresses are continuous.  These transactions are defined as Host Memory Read, Host Memory Write, and Host Command Write. Each transaction consists of a command phase and a data phase. The Host Command Write only has a command phase. Bit assignments for these commands are defined in the FT800 Programmers Guide. Where it is noted on the following slides to “write a register”, “write a display list” or similar, these three commands are used to accomplish the task.