The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches either of these thresholds. The first threshold is the FIFO almost full threshold. The value in this register corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO crosses this threshold limit, an interrupt to the CPU is generated so the chip can enter the TX mode to transmit the contents of the TX FIFO. The second TX threshold is the FIFO almost empty threshold. When the data being shifted out of the TX FIFO drops below the almost empty threshold, an interrupt will be generated. The microcontroller will need to switch out of the TX mode or fill more data into the TX FIFO. The transceiver can be configured so that when the TX FIFO is empty it will automatically exit the TX state and return to one of the low power states. When TX is initiated, it will transmit the number of bytes programmed into the packet length field. When the packet ends, the chip will return to a state specified in the registers; for example, the STANDBY or READY state. The RX FIFO has one programmable threshold which is called the FIFO almost full threshold. When the incoming RX data crosses the almost full threshold an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.