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Image of MoSys Accelerator Bandwidth Engine: High Performance/High Bandwidth - Single-Chip Buffering

The performance, or throughput, of a Peraso accelerator engine device can be “tuned” by selection of the SerDes frequency, the number of SerDes lanes utilized and the selected Burst size. The vertical axis shows the effect of number of lanes used and Burst length while the horizontal reflects the SerDes rate used. The value pictured in the boxes is the value of the data throughput so in the case of a 16 lane, Burst of 8 to 25Gbps device, the value is 320. This reflects the fact that 320Gbps of data is transferred. This has already taken out the overhead of the protocol. So, this is pure data throughput. Also, realize that this reflects 320Gbps at the ingress of the device and in addition, 320Gbps at the egress of the device which results in 640 total throughput of the device. In relation the blue, red, and green lines reflect the equivalent throughput of the RLDRAM, QDR IV, and Sigma Quad devices on the market.

PTM Published on: 2021-08-11