Shown here is the basic architecture that is used in the bandwidth engine products (BE2 and BE3). Beginning at the top of the slide, it is seen that the input of the devices are composed of two GCI ports. Each of these ports allow up to 8 SerDes lanes to be utilized and each lane is capable of supporting from 10Gbps up to 25Gbps, depending on the device. This interface is designed to be low latency and highly efficient, to allow for the large bandwidth that this family of products supports. In looking at the center of the diagram it can be seen that the memory in the device is segmented into four (independent) partitions, each of which can be thought of as separate 2M x 72b or 4M x 72b devices which reside in a common package. Part of the increased bandwidth of these devices is derived from the fact that these four partitions are capable of operating simultaneously and in parallel, enabling up to 4 times the bandwidth of a comparable memory device. In addition, by taking advantage of the optional in-memory functions there is an opportunity to boost system performance even more. As seen at the bottom of this slide, the results of the memory access are returned on a dual bus return structure that operates separately and in parallel with the input structure, allowing the throughput to be un-interrupted by the burden to perform operations of “bus-turnaround”. All of these features were designed to provide a designer with options to increase throughput without trading off system complexity.