The bandwidth engine family from Peraso is comprised of three semiconductor devices: the BE2 is a 576Mb device with I/O SerDes support at up to 12.5Gbps, the BE3 is a 1Gb device with I/O SerDes support at up to 25Gbps, and the PHE that has 1Gb of memory and also contains 32 eight-way threaded Risc cores, for a potential 256 threads. This family offers designers a wide variety of density and performance options to improve system bandwidth and performance. As an added support product, Peraso offers to provide or help design the RTL controller logic that would reside in either the host FPGA or ASIC.