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Image of MoSys Accelerator Bandwidth Engine: High Performance/High Bandwidth - PHE Architecture

To introduce the PHE device, this slide provides a general overview of its features. To explore the real power of this device it is suggested that contacting Peraso sales and/or applications will be a good next step. The PHE device is a 1Gb memory with 32 Risc Cores that are each up to 8-way threaded for a potential 256 threads. It is supported with the GCI interface that has up to 25Gbps SerDes and has the internal bandwidth to support 1.5Tb of data movement. This device is also pin compatible with the BE3 devices and can be considered an upgrade path for those using the base BE devices.

PTM Published on: 2021-08-11