In summary, Peraso’s partitioned, parallel array memories deliver the high capacity and low power of embedded DRAM (eDRAM) with the performance and ease of use of traditional (6T) SRAM. The 1T-SRAM memory technology is based on a dynamic bit cell that achieves a considerable size and soft error immunity advantage over six-transistor SRAMs (6T-SRAMs) and other conventional SRAM and QDR SRAM cells. Peraso embedded in-memory function accelerating memory represents breakthrough technology at the speed and size of the intelligent memory ICs. Now the customer can offload functions from the FPGA or processor to optimize system performance and improve functionality. IMFs range from fixed Burst/fixed RMW to fully programmable solutions enabling designers to customize the ideal memory IC for their specific application.