As a review of the previous slides, this slide lists the major points of the implementation of the Cortex-M3 on the SAM3U: the Cortex-M3 Revision 2 is embedded; clock gating to reduce power consumption in low-power modes is implemented; Memory Protection Unit is embedded; NVIC is implemented, without NMI, but providing thirty interrupts and sixteen priority levels. Debug level 3 and Trace Level 1 have been implemented; and there is no implementation of the Wakeup Interrupt Controller as the same feature is handled by the Supply Controller of the SAM3U.