In terms of performance, the SAM3U is the device suited to applications with intensive communication requirements, such as high-speed gateways in industrial, medical, data processing and consumer applications. First, the device is built around a high data bandwidth architecture with a 5-layer bus matrix, which means that each master can perform an access concurrently with others to an available slave. In addition, the SAM3U embeds a DMA controller acting as one matrix master. The DMA controller embeds four channels as follows: three channels with 8 Bytes/FIFO for Channel Buffering and one channel with 32 Bytes/FIFO for Channel Buffering. It supports linked list with status write back operation and can perform word, half-word or byte transfers. It handles high-speed transfer of SPI, SSC and HSMCI (peripheral to memory, memory to peripheral), memory to memory transfer and can be triggered by PWM and Timer Counter (which enables to generate waveforms though the External Bus Interface). Note that the high-speed USB has his own DMA channel acting as one matrix master too. There is also a 19-channel PDC (Peripheral DMA Controller) which handles data transfer between peripherals and memories. The internal SRAM is split in three blocks (32 kB for SRAM0, 16 kB for SRAM1 and 4 kB dedicated to the NAND flash controller on the SAM3U4) to obtain maximum bandwdith. The user can see SRAM0 and SRAM1 as contiguous. Note that if the NAND Flash controller is not used, these 4 kB of SRAM can be used as general purpose.