The internal SRAM was also designed to maintain a high bandwidth level when several high-speed peripherals are used simultaneously. The SRAM is split in three blocks: in the SAM3U one will find two blocks of 32 kB and 16 kB respectively and a 4 kB block (dedicated to the nandflash by default) which can be used as a generic SRAM if the nandflash controller is not used. These three blocks are seen as three separate slaves by the matrix, and thus can be accessed in parallel by different masters. This increases the general bandwidth compared to a single bank architecture. Note that the two largest SRAM blocks can be seen as contiguous by the core. The SRAM also contains thirty-two backup registers of 1 Byte each.