The next series of slides will look in detail at some of the features of the Cortex-M3 and their implementation on the SAM3U device – the SAM3U implementation is shown in red in the text. The first features the Nested Vectored Interrupt Controller on the Cortex-M3. The vectored interrupt feature means that software is not required to determine which IRQ handler to serve. With the NVIC, software code is not necessary to set up nested interrupts, as this is the default set up on the Cortex-M3 core. This also provides mechanisms to reduce interrupt latency as late arrival or tail chaining. As a consequence the interrupt latency is twelve cycles down to six cycles in the case of tail chaining, SAM7 was twenty-four to forty-two cycles. The core is designed to provide up to 240 external interrupt sources. For the SAM3U, up to thirty interrupt sources are available and sixteen priority levels. The SAM3U does not implement the non-maskable interrupt. There is also a System Tick, which is used by the RTOS as a scheduler.