This slide shows the key features of the Cyclone® III architecture and is a blueprint for the features that will be highlighted in the rest of this presentation. While this is a 65nm low power process, the core voltage is 1.2V. The highest density device contains 4Mb of RAM, divided into 9k blocks which were optimized for video buffering and other RAM intensive applications. In the largest device, there are 432 of these blocks that can be configured as single port, dual port, or true dual port RAM or ROM. The devices also support both parallel and serial configurations which eliminates the need for an external microcontroller if remote access upgrades are necessary. In addition to increasing the RAM and DSP, the onboard PLLs are being upgraded to a Stratix-class PLL. They are now dynamically reconfigurable in system, and feature up to 5 outputs. The larger devices have 4 PLLs while the two smaller devices have 2 PLLs each.