Cyclone® III designs combine more clocks into a single PLL when compared to Cyclone® II designs through the use of 2 additional output counters. The smallest phase shift is determined by the Voltage Control Oscillator (VCO) period divided by 8. For degree increments, Cyclone® FPGAs can shift output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the multiplication/division ratio needed on the PLL output clock. The main goal of a PLL is to synchronize the phase and frequency of an internal/external clock to an input reference clock. There are a number of components that comprise a PLL to achieve this phase alignment. Cyclone® PLLs align the rising edge of the reference input clock to a feedback clock using a phase-frequency detector (PFD). The falling edges are determined by the duty cycle specifications. The PFD produces an up or down signal that determines whether the VCO needs to operate at a higher or lower frequency.