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Cyclone3-Slide25

A key area of focus for the Cyclone® III device family was optimizing memory to logic ratios for key high-volume, cost sensitive applications. Based on extensive customer design analysis and simulation, the on-chip blocks in Cyclone® III devices have been increased to 9kB including parity bits. The performance was also increased from 216MHz to 260MHz. Other features were added to increase flexibility and ease of use of the features. For example, Cyclone® III adds the ability to provide new data or old data when performing a read during write operation in Dual-Port mode. Quartus® II software can take advantage of the extra clock enables to reduce power by shutting off parts of the memory block when not in use.

PTM Published on: 2011-10-14