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Cyclone3-Slide12

The larger memory blocks enable: performance enhancements by reducing the need to cascade memory blocks, higher memory to logic ratios allowing users to select a smaller and lower cost device for memory intensive applications such as packet processing or processor code storage, and better memory to multiplier ratio for video line buffers and to support DSP intensive applications such as general video and image processing. Memory bandwidth is defined as Memory Blocks x ports (2 per) x width of ports (36b) x Frequency (260MHz). If the Cyclone® III is compared with the Cyclone® II: the Cyclone® III’s blocks are increased, frequency has increased, and port width is the same, leading to a significant increase in memory bandwidth.

PTM Published on: 2011-10-14