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Cyclone3-Slide36

To summarize the Cyclone® III clocking and PLL advantages over the Cyclone® II: the outputs per PLL are increased from 3-5 to gain 8 additional PLL generated clocks, the total number of clocks was increased from 8-16 to 10-20 clocks per device, and the operating frequency was extended on the lower end to support low-cost clocks and on the higher end for higher performance devices. Additionally, the PLLs can be dynamically configured with values stored in the M9K blocks, and can be cascaded to save I/Os and ease PCB routing by eliminating the need to bring the clock off the chip and back to the device. The Cyclone® III also enables an auto-calibration feature on DDR interfaces for higher performance and an easier timing closure process.

PTM Published on: 2011-10-14