In order to support the dense logic structure of Cyclone® III FPGAs, these devices have either 10 or 20 global clocks, depending on device density. The global clock mux was completely re-structured to enable many of the new PLL features, as well as for memory interface timing. The PLLs on the Cyclone® III series are low jitter, very flexible PLLs that each offer up to 5 outputs. The frequency range now extends to as low as 5MHz and as high as 440MHz clock input signals. Another change that was made was the addition of dynamically controllable frequency and phase of the PLLs while the system is running. The PLLs can now also be cascaded together to get even more granularity on the clock frequency generated.