The DSP block supports the following features: a base cell containing an 18b by 18b multiplier feature, one full-precision (36 bit) 18b by 18b multiplier output capability to split the base cell containing one 18b by 18b multiplier into a cell containing two 9b by 9b multipliers, two full-precision (18 bits each) 9b by 9b multiplier outputs, and I/O registers to improve block speed. The DSP block is targeted for 260MHz 18b by 18b multiplication with both registers engaged, and with the fastest speed grade. Input register banks can be set/bypassed in 9b chunks. Similarly, the output register banks can be set/bypassed in 18b chunks. 2 dynamic input signals (SIGNX and SIGNY) have input registers that can be set/bypassed independently of the data register banks.