The ECC on the F28M35x is a single error correction, double error detection type. What that means is that if a single error is detected, it will be corrected, and it will be corrected without any performance loss on either the flash or the RAM. If there is double error detection, then that would be considered an uncorrectable error just as the parity error is an uncorrectable error, and the same type of failure response would then occur. An NMI to the respective CPU and the error detected is then logged. Even with the single-bit error detection and correction the designer still has the option to either ignore that a correction occurred or to have a counter incremented so that the number of errors can be kept track of and the user can then set a threshold level to cause an interrupt on the CPU after a particular number of errors have occurred. The user could then take the corrective action that the application requires. There might situations where even though it is corrected, the user might want to set the threshold level to a level of one and save the logged information about where the error occurred. Also the user might want to save that to memory and to keep kind of a black box data recorder of where the errors has occurred. That might be a pretty good strategy to building a safety diagnostics into the system. ECC is available for both RAM and flash. For the RAM, it is available for the dedicated RAM blocks of C0 and C1 and for the M3 and C28, the L0, L1, M0 and M1 blocks. M0 and M1 are the typical location for the C28 stack, it makes sense to have ECC for these locations. The ECC for RAM covers both data and address. There are seven bits of ECC code bits for the upper 16 bits of data and seven bits for the lower 16 bits of data and then seven bits for the address. That gives the ability to be able to have a single error and be able to correct for it and to be able to detect two errors. Again, this is a single cycle access to either 16 or 32-bit reads or writes. The ECC does not reduce the performance, not at all. The Boot INIT, as was mentioned on an earlier slide, at power up, there’s a RAM INIT function that initializes the RAM so that there is not going to be ECC errors at power up. The ECC code bits are initialized along with the data bits. Finally, the ECC for flash also covers the data and address, as well. There is eight bits for the upper 64-bits of data and eight bits for the lower 64-bits of data. The performance for flash with ECC enabled is 25 nanosecond access time, so it’s 40MHz for zero wait state access. The Concerto family has a 128-bit wide two-level pre-fetch buffer. On previous 28x devices, it was 64 bits wide, so this has been doubled. Essentially it is eight 16-bit or four 32-bit instructions. To help with the through put there is an eight byte data cache that has been added.